Modern computer systems and data processing systems make high demands on the data memories used therein. These memories should be capable of providing extensive data within the shortest possible access time. Fast data memories meeting these requirements are data memories with integrated electronic memory devices such as, for example, so-called DRAM (Dynamic Random Access Memory) chips.
Often, however, memory capacities are demanded which cannot be fulfilled by a single device. A number of memory devices are therefore embedded in familiar manner in a high-capacity memory system. The individual memory device must therefore cooperate with memory controllers and/or other memory devices, ensuring interference-free and time efficient coordination of the data flow. The memory systems comprise a large number of individual memory devices which are produced in high numbers with the aid of complex and highly developed production processes.
In conventional memory systems comprising a number of memory devices, a read request, for example, can be delivered to all memory devices, to a group of memory devices or to a single memory device, wherein the corresponding memory device then outputs the requested data. The individual memory device stores the data in a memory cell array which may require a characteristic time, the latency period, for outputting the requested data. The latency period is thus defined herein as the time interval from the provision of corresponding drive signals to a memory cell array to the actual availability of the requested data.
In spite of the high and optimized reproducibility of established production processes, it is impossible to produce identical devices. Instead, the individual devices are subject to process-related variances which become noticeable mainly with regard to a latency period varying from device to device. Furthermore, fluctuations in the supply voltage and the ambient temperature during the operation also lead to a change in latency period. The said variances are also collectively referred to as PVT (Process Voltage Temperature) variances. The time interval between the request and the reception of the data thus varies.
This varying latency period, which may not be easily controlled per se, in known memory devices may lead to certain restrictions with regard to the time efficiency in the interaction of a number of memory devices: to increase the number of memory devices in a memory system—and thus also the total memory capacity—while simultaneously minimizing the effective access time. The individual memory device should be capable of providing the requested data reliably after a well defined latency period which is constant over the entire operation. If, furthermore, a number of memory devices use a common data bus for outputting the data, for example, when cascaded together, it may become necessary that the individual memory device inserts the data into a data stream at a well defined and determinable time. Otherwise, collisions occur when a memory device outputs data at a time at which data signals are already present at the location of the signal entry. Furthermore, too generous a waiting time between two successive read requests can lead to inadequate loading of the signal path.